1. Field of the Invention
This invention relates to a semiconductor memory device and method for manufacturing it. The invention is particularly related to a dynamic random access memory (to be referred to as a dynamic RAM hereinafter).
2. Description of Invention Background
Recently, a number of methods which decrease the size of semiconductor integrated circuit elements have been tried to increase packaging density. For example, in dynamic RAMs, MOS capacitors which store data are formed by a parallel combination of two capacitors. One capacitor is formed between an electrode and an inversion region (with anooxidation area therebetween), and another capacitor is formed between the inversion region and a semiconductor substrate. However, since the capacitance is small in this configuration, the area of the memory cell must be large to obtain a large capacitance.
As shown in FIGS. 1 and 2, a memory cell structure of reduced size which removes these faults is illustrated in "The Hi-C RAM Cell Concept" IEEE, ED-25, No. 1, JANUARY 1978, P88 by ALF, TASCH. FIG. 1 is a sectional structure drawing. FIG. 2 is an equivalent circuit of FIG. 1. As shown in FIG. 1, a P type semiconductor substrate 11 consists of, for example, silicon. The doping concentration of substrate 11 is 2.times.10.sup.15 cm.sup.-3. A N.sup.+ type source region 12 and a N.sup.+ type drain region 13 are formed in semiconductor substrate 11. A gate electrode 16 is formed on an insulation layer 15 which is formed on a channel region 14 between source and drain regions and 13. The result is an insulation gate type field effect transistor Q. Source and drain regions and 13 are respectively formed by doping with having arsenic a concentration of 10.sup.20 cm.sup.-3.
MOS capacitor C is formed adjacent to source 12. MOS capacitor C includes a P.sup.- type impurity region 17 adjoining source region 12, N.sup.+ type impurity region 18 which has a shallow diffusion depth and is formed in impurity region 17, an insulation layer 19 formed on N.sup.+ type impurity region 18 and a polycrystalline silicon gate 20 formed on insulation layer 19. Drain region 13 is connected to a bit line BL, gate electrode 16 is connected to a word line WL and polycrystalline silicon gate 20 is connected to a negative power supply Vs or positive power supply.
In the above configuration, the memory capacitance results from a parallel capacitance of PN junction capacitance Cj between P.sup.- type impurity region 17 and N.sup.+ type impurity region 18 and an oxide capacitor Ci including insulating layer 19 between polycrystalline silicon gate 20 and N.sup.+ type impurity region 18. For this structure, the capacitance value per unit area can be increased and chip area can be reduced.
However, in the above structure, when alpha particles penetrate the surface of semiconductor substrate 11, it can create a significant number of electron-hole pairs near a storage node. Electrons, as minor carriers of the electron-hole pairs, are absorbed in N.sup.+ source region 12 to erroneously cause the memory data to change from "1" to "0" (i.e., a soft error). Also, when the memory cell is selected and transistor Q is conductive, the electrons created by the alpha particle radiation are absorbed in N.sup.+ impurity region 18 through drain region 13, channel region 14 and source region 12 causing the memory data to erroneously change from "1" to "0".
Furthermore, the concentration of source region 12 is higher than that of N.sup.+ impurity region 88. As a result, impurities are diffused in the lateral direction when source region 12 is formed. Therefore, N.sup.+ type impurity region 12' diffuses into P.sup.- type impurity region 17 as illustrated in FIG. 3. As a result, the contact area between P.sup.- type impurity region 17 and N.sup.+ type impurity region 18 is decreased, decreasing the memory capacitance.